TimeHawk simplifies the debugging process through trial-and-error methods. After a design is loaded, it can be modified by any typed in SDC commands through TimeHawk Tcl shell. Then an updated analysis can quickly tell if the modification has fixed the timing bug.
Besides providing the signoff-style timing report, TimeHawk Constraints also checks and verifies for all type of constraints, especially for
2. Case analysis statements
3. Path exceptions
4. I/O constraints
5. Checks binned by hierarchy
identify timing violations introduced by missing or improper constraints.
The unique CTS technology of TimeHawk Constraints utilizes the powerful gate-level timing engine to identify the missing constraints without the actual placement and CTS, reducing the iterations time by three to four weeks. In addition, our technology may also utilize the physical information from the floorplan and placement stage, create hybrid models to improve the completeness and validity of timing constraints.
There is no need to learn complex commands. If the user understands SDC and is familiar with timing reports, he or she can learn the debugger in minutes.
Reuse of internal or external IP blocks enable the fast development of SoCs today. However, timing constraints often come from various sources, where mismatch could slow down the process of integration, clean up and validation. Improper timing constraints and budgets that are not detected earlier may lead to extra P&R iteration, longer optimization time, or even chip failure. Existing tools either check constraints at RTL and registers without timing information, or have to wait overnight or days for a gate-level signoff STA. TimeHawk Constraints closes the gap. Dedicated interactive debugging features, in combination with our powerful TimeHawk signoff timing engine, are capable of analyzing full chip timing result even faster than RTL-only debug tools.
Compare with other formal-based constraint tools, TimeHawk Constraints in addition identifies timing problems with full timing results. Instead of just checking on constraints, it shows an entire timing picture, and provides early identification of:
1. Unrealizable timing budget
2. Hard-to-meet paths
3. Unnecessary exceptions
4. Inter-IP paths
5. Clock latencies
With the hundreds and thousands of clocks in today's designs, the designers may take weeks of iterations to perform the placement and CTS optimizations, then
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