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- Full support for SDC 2.0
- CSM accuracy
- Signal Integrity
Fast and accurate timing analysis shortens ECO iterations. TimeHawk provides not
- Path based analysis
- High capacity for flat timing analysis
- Verilog netlist (.v)
- Timing library (.lib)
- Parasitic format (.spef)
- Timing constraint (.sdc)
- Compressed format (.gz, .tar)
- Critical path reports
- Pin constraint violation
- Hawkeye MMMC analysis report
- ETM models
TimeHawk is an independent timing solution which can be integrated into any backend flow with a simple setup. All input data are available from backend flow, and a simple script is sufficient to start the process. TimeHawk also provides MMMC compatible GUI and result extraction scripts. Once setup, the user only needs to push a button and it works for rest of the iterations.
TimeHawk applies proprietary electronic signal analysis algorithms and advanced software architecture to the traditional STA problem, especially in the fast analysis of the current-source based delay model.
For the convenience of our customers, the system is architected to operate on the most commonly available computer hardware which is the single-box multi-core CPUs. For customers with cluster based computer framework, TimeHawk can be distributed on multiple nodes for MMMC computations to utilize the resources.
only timing results, but also MMMC scenarios based heuristics to detect the potential instance or path segments that user should consider to perform ECO.
For many years, the industry's leading signoff experts have known that many timing factors, such as library characterization models, variation models, may easily cause timing differences, but are not fully considered in commercial STA tools. The common practise is to add a pessimism margin to cover these effects. Our unique artificial intelligence approach, brings unprecendent SPICE correlation for STA. It does the best to reduce timing pessimism, and provide an easy approach to model different factors in various applications, such as signoff and DFM.
TimeHawk Static Timer is a groundbreaking STA solution for digital backend flow. It delivers SPICE-correlated timing results with an unbeatable speed. It can finish any of today's digital designs in minutes.
STA causes the most significant delay in backend iterations. TimeHawk opens up the bottleneck, and speeds up the design flow. Combined with our robust support for incremental SPEF update, it reduces backend iteration time by more than 50%.